Magnetic random access memory (MRAM) is a new memory technology that will likely provide a superior performance over existing semiconductor memories including flash memory and may even replace hard disk drives in certain applications requiring a compact non-volatile memory device. In MRAM bit of data is represented by a magnetic configuration of a small volume of ferromagnetic material and its magnetic state that can be measured during a read-back operation. The MRAM typically includes a two-dimensional array of memory cells wherein each cell comprises one magnetic tunnel junction (MTJ) (or magnetoresistive (MR)) element that can store at least one bit of data, one selection transistor (T) and intersecting conductor lines (so-called 1T-1MTJ design).
Conventional MTJ element represents a patterned thin film multilayer that includes at least a pinned magnetic layer and a free magnetic layer separated from each other by a thin tunnel barrier layer. The free layer has two stable directions of magnetization that are parallel or anti-parallel to the fixed direction of the magnetization in the pinned layer. Resistance of the MTJ depends on a mutual orientation of the magnetizations in the free and pinned layers and can be effectively measured. A resistance difference between the parallel and anti-parallel states of the MTJ can exceed 600% at room temperature.
The direction of the magnetization in the free layer may be changed from parallel to anti-parallel or vice-versa by applying two orthogonal magnetic fields to the selected MTJ, by passing a spin-polarized current through the selected junction in a direction perpendicular to the junction plane, or by using a hybrid switching mechanism that assumes a simultaneous application of the external magnetic field and spin-polarized current to the selected MTJ. The hybrid switching mechanism looks the most attractive among all others since it can provide good cell selectivity in the array, relatively low switching current and high write speed.
FIGS. 1A and 1B show a schematic cross-sectional and top down views of MRAM cell 10 employing the hybrid switching mechanism according to a prior art disclosed in U.S. Pat. No. 7,006,375 (Covington). The cross-section was taken alone the line 1A-1A shown in the FIG. 1B. The memory cell 10 includes a semiconductor wafer 11 with a selection transistor 12, MTJ element 21, a word line 16 and a bit line 19 that are orthogonal to each other (1T-1MTJ design). The bit line 19 and the MTJ element 21 are connected in series to a source region 13 of the selection transistor 12. The MTJ element 21 includes a pinned magnetic layer 22 with a fixed in-plane magnetization direction (shown by an arrow), a free magnetic layer 23 with a changeable in-plane magnetization direction (shown by arrows), a thin tunnel barrier layer 24 positioned between the free 23 and pinned 22 layers, and a pinning anti-ferromagnetic layer 25 exchange coupled with the pinned layer 22. The MTJ element 21 has an elliptical shape with a major axis of the ellipse being oriented in parallel to the word line 19. An easy magnetic axis of the pinned and free layers coincides with the major axis. The transistor 12 comprises a gate 15 having a width W of about a width F of the MTJ element 21 (W=F). A drain region 14 of the transistor 12 is connected to a ground line 18 through a contact plug 17.
To write a data to the MTJ element 21, a bias electric current IB is applied to the bit line 19. The current IB induces a magnetic bias field HB that affects the free layer 23 along its hard magnetic axis. The field HB forces the magnetization direction in the free layer 23 from its equilibrium state that is parallel to the major axis of the MTJ element 21. By applying a voltage to the gate 15 through the word line 16 the selection transistor 12 can be turned on. The transistor 12 delivers a spin-polarized current Is to the MTJ element 21. The current IS running through the element 21 produces a spin momentum transfer that together with the bias field HB provides a reversal of the magnetization direction in the free layer 23. The magnetization direction in the free layer 23 is controlled by a direction of the spin-polarized current Is. Magnitude of the spin-polarized current Is required to reverse the magnetization in the free layer 23 depends on the strength of the bias field HB that tilts the magnetization direction in the free layer relatively its equilibrium state. The switching current Is can be reduced more than twice by the relatively small bias magnetic field HB.
The MTJ with in-plane magnetization direction requires a high magnitude of the switching current Is even with applied magnetic bias field HB. Magnitude of the spin-polarized current Is defines a write speed of the memory cell; the speed increases with the current. The spin-polarized current Is of the cell 10 is limited by a saturation current of the transistor 12 that is proportional to a gate width W. The selection transistor 12 has the gate width W=comparable to the width F of the elliptical MTJ element 21. This gate width is incapable to deliver the required magnitude of the current Is. To overcome the above obstacles the gate width W of the transistor 12 needs to be substantially increased. However that will result in considerable increase of memory cell size and in MRAM density reduction.
Majority of the current MRAM designs uses the free and pinned layers made of magnetic materials with in-plane anisotropy. The in-plane MRAM (i-MRAM) suffers from a large cell size, low thermal stability, poor scalability, necessity to use MTJ with a special elliptical shape, and from other issues, which substantially limit a possibility of i-MRAM application at technology nodes below 90 nm.
MRAM with a perpendicular direction of the magnetization in the free and pinned layers (p-MRAM) does not suffer from the above problems since perpendicular magnetic materials have a high intrinsic crystalline anisotropy. The high anisotropy provides the p-MRAM with the excellent thermal stability and scalability, and with a possibility to use junctions of any shape. Nevertheless the existing p-MRAM designs have a large cell size and require a relatively high switching current.
What is needed is a simple design of p-MRAM having a high switching speed at low current, small cell size, high capacity and excellent scalability.